The present invention relates generally to the field of memory devices, and more specifically to a ferroelectric memory device structure, which provides a simple sensing scheme, and an accurate reference voltage for a sense amplifier used for sensing a 1T1C cell of an FeRAM array.
Several trends exist presently in the semiconductor device fabrication industry and the electronics industry. Devices are continuously getting smaller and requiring less power. A reason for these trends is that more personal devices are being fabricated which are relatively small and portable, thereby relying on a small battery as its primary supply source. For example, cellular phones, personal computing devices, and personal sound systems are devices which are in great demand in the consumer market. In addition to being smaller and more portable, personal devices are requiring more computational power and on-chip memory. In light of all these trends, there is a need in the industry to provide a computational device, which has memory and logic functions, integrated onto the same semiconductor chip. Preferably, this memory will be configured such that if the battery dies, the contents of the memory will be retained. Such a memory device which retains its contents while power is not continuously applied thereto is called a non-volatile memory. Examples of conventional non-volatile memory include: electrically erasable, programmable read only memory (xe2x80x9cEEPROMxe2x80x9d) and FLASH EEPROM.
A ferroelectric memory (FeRAM) is a non-volatile memory which utilizes a ferroelectric material, such as strontium bismuth tantalate (SBT) or lead zirconate titanate (PZT), as a capacitor dielectric situated between a bottom electrode and a top electrode. Both read and write operations are performed for an FeRAM. The memory size and memory architecture affects the read and write access times of an FeRAM. Table 1 illustrates exemplary differences between different memory types.
The non-volatility of an FeRAM is due to the bistable characteristic of the ferroelectric memory cell. An FeRAM cell may be selected by two concurrent X and Y voltage pulses, respectively, wherein X and Y correspond to a specific bit line and word line, respectively, identified by horizontal and vertical decoder circuitry. The FeRAM cells of the capacitor array which receive only one voltage pulse remain unselected while the cell that receives both an X and Y voltage signal flips to its opposite polarization state or remains unchanged, depending upon its initial polarization state, for example. Two types of ferroelectric memory cells are used commonly, a single capacitor memory cell and a dual capacitor memory cell. The single capacitor memory cell (referred to as a 1T1C memory cell) requires less silicon area (thereby increasing the potential density of the memory array), but is less immune to noise and process variations. Additionally, a 1T1C cell requires a voltage reference for determining a stored memory state.
The dual capacitor memory cell (referred to as a 2T2C memory cell) requires more silicon area, and it stores complementary signals allowing differential sampling of the stored information. The 2T2C memory cell is more stable than a 1T1C memory cell. As illustrated in prior art FIG. 1, a 1T1C FeRAM cell 10 includes one transistor 12 and one ferroelectric storage capacitor 14. A bottom electrode of the storage capacitor 14 is connected to a drain terminal 15 of the transistor 12. The 1T1C cell 10 is read from by applying a signal to the gate 16 of the transistor (word line WL)(e.g., the Y signal), thereby connecting the bottom electrode of the capacitor 14 to the source of the transistor (the bit line BL) 18. A pulse signal is then applied to the top electrode contact (the drive line or plate line PL) 20. The potential on the bitline 18 of the transistor 12 is, therefore, the capacitor charge divided by the bitline capacitance. Since the capacitor charge is dependent upon the bistable polarization state of the ferroelectric material, the bitline potential can have two distinct values. A sense amplifier (not shown) is connected to the bitline 18 and detects the voltage associated with a logic value of either 1 or 0 associated with the FeRAM polarization. Frequently the sense amplifier reference voltage is a ferroelectric or non-ferroelectric capacitor connected to another bitline that is not being read. In this manner, the memory cell data is retrieved.
A characteristic of a ferroelectric memory is that a read operation is destructive in some applications. The data in a memory cell is then rewritten back to the memory cell after the read operation is completed. If the polarization of the ferroelectric is switched, the read operation is destructive and the sense amplifier must rewrite or restore (onto that cell) the correct polarization value as the bit just read from the cell. This is similar to the operation of a DRAM. If the drive line voltage was small enough not to switch the ferroelectric then the read operation was not destructive. In general, a non-destructive read requires a much larger capacitor than a destructive read and, therefore, requires a larger cell size.
As illustrated, for example, in prior art FIG. 2, a 2T2C memory cell 30 in a memory array couples to a bit line (xe2x80x9cbitlinexe2x80x9d) 32 and an inverse of the bit line (xe2x80x9cbitline-barxe2x80x9d) 34 that is common to many other memory types (for example, static random access memories). Memory cells of a memory block are formed in memory rows and memory columns. The 2T2C ferroelectric memory cell comprises two transistors 36 and 38 and two ferroelectric capacitors 40 and 42, respectively. The first transistor 36 couples between the bitline 32 and a first capacitor 40, and the second transistor 38 couples between the bitline-bar 34 and the second capacitor 42. The first and second capacitors 40 and 42 have a common terminal or plate (the plate line PL) 44 to which a signal is applied for polarizing the capacitors.
In a write operation, the first and second transistors 36 and 38 of the 2T2C ferroelectric memory cell 30 are enabled (e.g., via their respective word line 46) to couple the capacitors 40 and 42 to the complementary logic levels on the bitline 32 and the bitline-bar line 34 corresponding to a logic state to be stored in memory. The plate line common terminal 44 of the capacitors is pulsed during a write operation to polarize the 2T2C memory cell 30 to one of the two logic states.
In a read operation, the first and second transistors 36 and 38 of the 2T2C memory cell 30 are enabled via the word line 46 to couple the information stored on the first and second capacitors 40 and 42 to the bar 32 and the bitline-bar line 34, respectively. A differential signal (not shown) is thus generated across the bitline 32 and the bitline-bar line 34 by the 2T2C memory cell 30. The differential signal is sensed by a sense amplifier (not shown) which provides a signal corresponding to the logic level stored in memory.
FIG. 3 illustrates an array portion 200 of the 1T1C memory cell structure as described for FIG. 1. The array 200 has a plurality of element groupings which operate together in a modular fashion to read and write to memory cells. FIG. 3, for example, shows two element groupings, in which each grouping comprises a sense amplifier (210 or 215) to sense a memory cell associated with a pair of bitlines (B1 220 and B1-bar 222, or B2 224 and B2-bar 226), which is accessed by one of a plurality of word lines (W1-W4) and plate lines (PL1-PL4), with each wordline accessing a 1T1C memory cell 240. One element grouping, for example, comprises a sense amplifier 210, coupled to a pair of bitlines B1 220 and B1-bar 222 through a set of bitline isolation transistors 230 controlled by an isolation switch line 235, to permit isolation from the sense amplifier 210, and a memory cell 240. The 1T1C memory cell 240 is comprised of a pass gate transistor 242 and a ferroelectric capacitor 244, which is accessed by its respective word line 246, and plate line 248.
In the same way, FIG. 4 illustrates an array portion 300 of the 2T2C memory cell structure as described for FIG. 2. The array 300 has a plurality of element groupings which operate together in a modular fashion to read and write to memory cells. FIG. 4, for example, shows two element groupings, in which each grouping comprises a sense amplifier (310 or 315) to sense a memory cell associated with a pair of bitlines (B1 320 and B1-bar 322, or B2 324 and b2-bar 326), which is accessed by one of a plurality of word lines (W1-W4) and plate lines (PL1-PL4), with each wordline accessing a 2T2C memory cell 340. One element grouping, for example, comprises a sense amplifier 310, coupled to a pair of bitlines B1 320 and B1-bar 322 through a set of bitline isolation transistors 330 controlled by an isolation switch line 335, to permit isolation from the sense amplifier 310, and a memory cell 340.
The 2T2C memory cell 340 is comprised of a pair of 1T1C type cells, with one coupled to the B1 bitline 320, and the other coupled to the B1 bitline-bar 322. The 2T2C memory cell 340, thus comprises two pass gate transistors and two ferroelectric capacitors. One pass gate transistor 342 is operable to couple ferroelectric capacitor 344 to B1 bitline 320, when accessed by the W1 word line 346, and PL1 plate line 348, while another pass gate transistor 346 is operable to couple ferroelectric capacitor 348 to B1-bar (bitline-bar 322), when accessed by its respective word line 346, and plate line 348.
Currently, most FeRAM memory arrays apply the 2T2C cell structure, because of the difficulties involved with supplying an accurate reference voltage to the sense amplifier of the 1T1C cell.
As shown by the sensing scheme response plots 400 of FIG. 5, the 2T2C cell sensing scheme 410 is generally easy to implement, as the sense amplifier compares a charge driven from a bitline/bitline-bar at a xe2x80x9c1xe2x80x9d state 412 with a charge driven from a bitline-bar/bitline at a xe2x80x9c0xe2x80x9d state 414. The opposite state conditions on the bitline inputs to the sense amplifier, eliminate the need for an exacting reference voltage level.
The 2T2C sensing scheme plot 410, begins at a time t0 416, at a xc2xd VCC level, where the pass gate transistors (e.g., 342 and 346 of FIG. 4) couple their respective FeRAM capacitors (e.g., 344 and 348 of FIG. 4) to their respective bitlines (e.g., B1 320 and B1-bar 322 of FIG. 4), to produce the bitline charging plots 412 (the xe2x80x9c1xe2x80x9d state bitline) and 414 (the xe2x80x9c0xe2x80x9d state bitline), between times t0 416 and tSENSE 418. At time tSENSE 418, the charge voltage on the bitlines is affected by the sensing operation of the sense amplifier, and changes the voltages as shown, and as discussed previously. Also as discussed, the states on the memory cells which were read must be re-written into the array, because of this charge altering read operation. However, the 2T2C cell needs twice as much area as the 1T1C cell.
Also shown in the sensing scheme response plots 400 of FIG. 5, is the 1T1C cell sensing scheme plots 420 and 430. The read response to a xe2x80x9c1xe2x80x9d state sensing operation is illustrated by plot 420, while the read response to a xe2x80x9c0xe2x80x9d state sensing operation is illustrated by plot 430. The 1T1C cell sensing generally is not easy to implement, as the sense amplifier must compare the read sense charge voltage produced by a target memory cell on one bitline/bitline-bar 422 or 434, to a reference voltage generated on the other bitline-bar/bitline 424 or 432.
The 1T1C sensing scheme plot 420, begins at a time t0 426, at a xc2xd VCC level, where the pass gate transistor (e.g., 242 of FIG. 3) couples FeRAM capacitor (e.g., 244 of FIG. 3) to bitline (e.g., B1 220 of FIG. 3), to produce the bitline charging plots 422 (if a xe2x80x9c1xe2x80x9d state is sensed on the bitline) and 434 (if a xe2x80x9c0xe2x80x9d state is sensed on the bitline), between times t0 416 and tSENSE 418. Prior to sensing at time tSENSE 418, a reference voltage must be present, as indicated by line segment 426.
Relative to the xe2x80x9c1xe2x80x9d state sensing 422 of the plot 420, the reference 426 produced on the bitline opposite the read sensing of the memory cell, must be more negatively offset 428 as shown. Relative to the xe2x80x9c0xe2x80x9d state sensing 434 of the plot 430, the reference 436 produced on the bitline opposite the read sensing of the memory cell, must be more positively offset 438 as shown. As with the 2T2C cell sensing scheme, at time tSENSE 418, the charge voltage on the bitlines is affected by the sensing operation of the sense amplifier, and changes the voltages as shown, and as discussed previously. Also as discussed, the states on the memory cells which were read must be re-written into the array, because of this charge altering read operation. However, the 2T2C cell needs twice as much area as the 1T1C cell. Thus one difficulty for the 1T1C cell sensing scheme is the need for generating an accurate reference voltage level.
Without a precise reference voltage level, the sensing which is done by the sense amplifier will not be able to accurately sense the xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d states with an adequate margin of certainty.
Similarly, the prior art DRAM cell sensing schemes of FIG. 6 illustrates the same essential differences between the 2T2C and the 1T1C cell sensing schemes. The sensing scheme response plots 500 of FIG. 6 demonstrate that the 2T2C cell sensing scheme 510 generally is easy to implement, as the sense amplifier compares a charge driven from a bitline/bitline-bar at a xe2x80x9c1xe2x80x9d state 512 with a charge driven from a bitline-bar/bitline at a xe2x80x9c0xe2x80x9d state 514. The opposite state conditions on the bitline inputs to the sense amplifier, again eliminates the need for generating an exacting reference voltage level, but the 2T2C DRAM cell sensing also requires double the area of the 1T1C cell sensing scheme.
In the 1T1C DRAM, between time t0 516 and tSENSE 518, the bitline (or bitline-bar) voltage increases or decreases depending on the cell state xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d, respectively. During this same time, reference voltage VREF of the bitline-bar (or the bitline) remains unchanged at the precharge level. Therefore, the sense amplifier connected to the bitline and bitline-bar can sense a xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d state by detecting the voltage difference between the two bitlines. In the case of the FeRAM, both the xe2x80x9c1xe2x80x9d and the xe2x80x9c0xe2x80x9d states will give the same direction voltage change, but with differing magnitudes. Therefore, the 1T1C xe2x80x9c1xe2x80x9d state response plot 520, and the xe2x80x9c0xe2x80x9d state response plot 530; demonstrate the same need for an exacting reference voltage for the DRAM as well as with the FeRAM.
Another prior art sensing scheme uses FeRAM xe2x80x9creference cellsxe2x80x9d or xe2x80x9cdummy cellsxe2x80x9d. The prior art reference cell includes 2 ferroelectric capacitors (FeCaps) that are fabricated generally identically to each other and to the array of memory cells. A prior art reference cell operates by charging one of the two FeCaps to a xe2x80x9c1xe2x80x9d state, and charging another to a xe2x80x9c0xe2x80x9d state, and allowing the two FeCaps to be coupled to a bitline and to charge share to create a reference voltage which is substantially half of that developed by a ferroelectric memory cell. Reference cells are only needed for certain memory cells, such as the 1T1C memory cells, that are not self-referenced, as with the DRAM or the 2T2C FeRAM sensing scheme. Although the prior art solves the problem of providing an accurate reference voltage for the 1T1C memory cells, a reference cell, or dummy cell comprising two FeCaps is used for each pair of bitlines.
Thus, conventional 2T2C FeRAM sensing schemes use excessive area for the applications considered. By contrast, conventional 1T1C cell sensing schemes, have only half the area, but require a means for generating an exacting reference voltage, and a more complex means of sensing.
Accordingly, there is a need for a simple sensing scheme for the 1T1C FeRAM memory cell, which senses the state of the cell with a greater margin of certainty, in a small low power solution.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Its primary purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The invention is directed to a ferroelectric memory structure for the 1T1C cell arrangement in an array of ferroelectric capacitor cells used in FeRAM memory applications. In particular, the device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target (selected) memory cell of the FeRAM array. The array of FeRAM memory cells store binary data in a ferroelectric capacitor, which is accessed by a transistor in the usual manner, but only requires the smaller area of the 1T1C cell arrangement.
Conventional FeRAM memory devices using 2T2C FeRAM sensing schemes require nearly twice the area on chip, and use therefore excessive area for the applications considered. On the other hand, conventional 1T1C cell sensing schemes require only half the area, but require a means for generating an exacting reference voltage, and a more complex sensing scheme.
Consequently, the solution according to the present invention is to make an accurate reference voltage from a reference circuit, wherein the reference voltage is a function of a plurality of FeRAM dummy cells, and make each of these dummy cells operable to be coupled to a plurality of selectable bitlines. The sensing scheme of the present invention utilizes this reference circuit to generate the reference voltage, apply the reference voltage to one of the bitline inputs of a sense amplifier, and apply the target memory cell sense voltage to the other bitline input of the sense amplifier. The sense amplifier can then accurately determine from the differential voltage, the state of the FeRAM memory cell with a large margin of certainty.
The dummy cell structure and the particular sensing scheme of the present invention provide a dummy cell with a single FeCap within each dummy cell for a pair of bitlines, thereby reducing the quantity of dummy cells. This is made possible by a dummy cell control circuit, which provides a means of coupling the FeCap (within the dummy cell) to a plurality of bitlines. Therefore, the FeCap is not dedicated to coupling to one particular bitline, but is able to be coupled to plurality of bitlines according to the invention.
Conventional bitline and word line decode logic may be used to select the FeRAM cell to be read. The reference circuit generates a reference voltage which is a function of a plurality of FeRAM dummy cells. Two bitlines neighboring the selected memory cell are coupled by a bitline shorting transistor in the reference circuit, wherein at least one of the plurality of FeRAM dummy cells is biased to a xe2x80x9c0xe2x80x9d state, and at least one of the plurality of FeRAM dummy cells is biased to a xe2x80x9c1xe2x80x9d state. As charge sharing takes place between the dummy cells via the shorted bitlines, an averaging of the charge takes place producing the reference voltage (e.g., about (P+R+S)/Cbit) which is substantially centered between the xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d states. A plurality of sense amplifiers receives a cell sense voltage from the selected memory cell on an associated bitline, and the reference voltage is received on another bitline input of the sense amplifier. Thus, a ferroelectric memory structure provides a centered reference voltage and a simple sensing scheme for the accurate sensing of the logic state of an FeRAM 1T1C memory cell for a read operation.
Another aspect of the invention provides a reference circuit that generates a reference voltage from the xe2x80x9c0xe2x80x9d state charge of a single dummy cell which is charge shared to a selected pair of bitlines or pair of bitline-bars of a plurality of bitlines. As with the 2 dummy cell method above, the single dummy cell method also provides a mechanism for coupling the dummy cell to a choice of multiple bitlines, but in addition, the single dummy cell method provides a means of coupling the dummy cell to multiple pairs of bitlines. For example, a two bitline, and a 4-bitline implementation are included, but the dummy cell implementation and method of this aspect of the invention may be applied to any number of bitlines of the array. Even though the reference voltage (e.g., about (P+R+S/2)/Cbit) of this aspect of the present invention may be somewhat less precise than the two dummy cell reference circuit, the reference voltage which is produced is still substantially half of that developed by a ferroelectric memory cell, and may be used to reduce the quantity of dummy cells needed in the array.
According to another aspect of the invention, bitline access transistors within the dummy cell are provided to couple the FeCap to a plurality of bitlines, and may therefore also serve double duty as bitline shorting transistors to short between a neighboring pair of bitlines or a pair of bitline-bars associated with the FeRAM dummy cell and the sense amplifier of the ferroelectric memory device.
In accordance with the present invention a ferroelectric memory device and a method of sensing an FeRAM 1T1C memory cell in a read operation of the same comprises an array of FeRAM memory cells associated with a target memory cell which is to be read. A bitline and a word line are used to address and access the target memory cell via conventional bitline and word line decode logic. A reference circuit generates a reference voltage which is substantially half that developed by a ferroelectric memory cell. The reference circuit comprises two dummy cells which generate the reference voltage as a function of charge sharing between two dummy cells charged to opposite binary states. Each dummy cell comprises an FeCap with a dummy plate line to access and charge the FeCap, and a pair of access transistors to select a pair of bitlines or a pair of bitline-bars associated with the target memory cell to couple with the FeCap.
When the target memory cell is accessed and polled by a plate line voltage, an associated sense amplifier receives a sense voltage from the target memory cell on one bitline, and the reference voltage on another of the selected bitline pair associated with the reference circuit and the target memory cell. The sense amplifier compares the sense voltage to the reference voltage to make a determination as to a logic state of the target memory cell during a read operation.
Thus a ferroelectric memory device structure is disclosed which provides a simple sensing scheme and an accurate reference voltage for a sense amplifier used for sensing a 1T1C cell of an FeRAM array.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.